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1 of 19 features ? real - time clock (rtc) keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years ? 128k x 8 nv sram directly replaces volatile static ram or eeprom ? embedded lithium energy cell maintains c alendar operation and retains ram data ? watch function is transparent to ram operation ? automatic leap year compensation valid up to 2100 ? full 10% operating range ? over 10 years of data retention in the absence of power ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? dip module only standard 32 - pin jedec pinout ? underwriters laborator ies (ul) recognized ( www.maxim - ic.com/qa/info/ul/ ) ? powercap module board only surface mountable package for direct connection to powercap containing battery and crystal replaceable battery (powercap) pin - for - pin compatible with ds1244p and ds1251p pin configurations encapsulated dip (740 - mil flush) rst n.c. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 dq2 gnd 15 16 18 17 v cc a15 we a13 a8 a9 a11 oe a10 ce dq7 dq5 d q6 dq4 dq3 ds1248 top view 1 rst 2 3 a15 a16 n.c. v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 n.c. x1 gnd v bat x2 powercap module board (uses ds9034pcx + powercap) ds1248p ds1248/ds1248p 1024k nv sram with phantom clock 19 -60 78 ; rev 11/11 downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 2 of 19 ordering information part temp range v cc range pin - package ds1248y-70+ 0c to +70c 5v 10% 32 edip ds1248y- 70ind+ - 40c to +85c 5v 10% 32 edip ds1248yp-70+ 0c to +70c 5v 10% 34 powercap* ds1248w-120+ 0c to +70c 3.3v 10% 32 edip ds1248w-120ind+ - 40c to +85c 3.3v 10% 32 edip ds1248wp-120+ 0c to +70c 3.3v 10% 34 powercap* ds1248wp-120ind+ - 40c to +85c 3.3v 10% 34 powercap* + denotes a lead (pb) - free/rohs - compliant package . * ds9034pcx + or ds9034i -pcx+ ( powercap) required. must be ordered separately. detailed description the ds1248 1024k nv sram with phantom clock i s a fully static, nonvolatile ram (organized as 128k words by 8 bits) with a built - in real - time clock. the ds1248 has a self - contained lithium energy source and control circuitry, which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically swi tched on and writes protection is unconditionally enabled to prevent garbled data in both the memory a nd real - time clock. packages the ds1248 is available in two packages: 32 - pin dip and 34 - pin powercap module. the 32 - pin dip style module integrates the crystal, lithium energy source, and s ilicon in one package. the 34 - pin powercap module board is designed with contacts for connection to a separat e powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1248p after completion of the surface mount process. mounting the p owercap after the surface mount process prevents damage to the crystal and battery because of the high t emperat ures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 3 of 19 pin description pin name function edip powercap 1 1 rst active - low r eset input. this pin has an internal pullup resistor connected to v cc . 2 3 a16 address inputs 3 32 a14 4 30 a12 5 25 a7 6 24 a6 7 23 a5 8 22 a4 9 21 a3 10 20 a2 11 19 a1 12 18 a0 23 28 a10 25 29 a11 26 27 a9 27 26 a8 28 31 a13 31 2 a15 13 16 dq0 data in/data out 14 15 dq1 15 14 dq2 17 13 dq3 18 12 dq4 19 11 dq5 20 10 dq6 21 9 dq7 22 8 ce active - low chip - enable input 24 7 oe active - low output - enable input 29 6 we active - low write - enable input 30 4, 33, 34 n .c. no connect 32 5 v cc power - supply input 16 17 gnd ground downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 4 of 19 ram read mode the ds1248 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specified by the 17 address inputs (a 0C a16) defines which of the 128k bytes of data is to be accessed. valid data will be available to the eight d ata - output drivers within t acc (access time) after the last address input signal is stable, providin g that ce and oe (output enable) access times a nd states are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe , rather than address access. ram write mo de the ds1248 is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (hig h) during write cycles to avoid bus contention. however, if the output bus has be en enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power - fail point, v pf (point at which write protection occurs), the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point, v so (b attery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below v pf , access to the device is inhibited. if v pf is less than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device p ower is switched from v cc to the backup supply (v bat ) when v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address signals must be powered down when v cc is p owered - down. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 5 of 19 phantom clock operation communication with the phantom clock is established by pattern recog nition on a serial bit stream of 64 bits, which must be matched by executing 64 consecutive write cyc les containing the proper data on dq0. all access es that occur prior to recognition of the 64 - bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles ei ther extract or update data in the phantom clock, and memory access is inhibited. data transfer to and from the timekeeping function is accomplished wit h a serial bit stream under control of chip enable, output enable, and write enable. initially, a read cyc le to any memory location using the ce and oe control of the phantom clock starts the pattern recognit ion sequence by moving a pointer to the first bit of the 64 - bit comparison register. next, 64 consecutive write cycles are executed usi ng the ce and we control of the smartwatch. these 64 write cycles are used only to gain access to the phantom clock. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just o ne address location in ram as a phantom clock scratch pad. when the first wr ite cycle is executed, it is compared to bit 0 of the 64 - bit comparison register. if a match is found, the pointer increment s to the next location of the comparison register and aw aits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle o ccurs at any time during pattern recognition, the present sequence is aborted and the comparison reg ister pointer is reset. pattern recognition continues for a total of 64 write cycles as described above u ntil all the bits in the comparison register have been matched (figure 1). with a correct match for 64 bits, th e phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 c ycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved w ith ce cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock. phantom clock register information the phantom clock information is contained in eight registers o f 8 bits, each of which is sequentially a ccessed 1 bit at a time after the 64 - bit pattern recognition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups o f 8 bits. writing and reading individual bits within a register could produce erro neous results. these read/write registers are defined in figure 2. data contained in the phantom clock register is in binary - coded decimal format (bcd). reading and writing the registers is always accomplished by stepping throu gh all eight registers, star ting with bit 0 of register 0 and ending with bit 7 of register 7. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 6 of 19 figure 1 . phantom clock register definition note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 7 of 19 figure 2 . phantom clock register definition am/pm/12/24 - mode bit 7 of the hours register is defined as the 12 - hour or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 C 23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the rst and oscillator functions. bit 4 controls the rst (pin 1). when the rst bit is set to logic 1, the rst input pin is ignored. when the rst bit is set to logic 0, a low input on the rst pin will cause the phantom clock to abort data transfer without changi ng data in the watch registers. bit 5 controls the oscillator. when set to l ogic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch becomes operational. these bits are shipped from the factory set to a logic 1. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 8 of 19 zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits, which will alway s read logic 0. when writing these locations, either a logic 1 or 0 is acceptable. bat tery longevity the ds1248 has a lithium power source that is designed to provide energy for clock activity and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1248 c ontinuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal clock oscillator running in the absence of v cc power. each ds1248 is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery - backup operation. actual life expectancy of the ds1248 will be mu ch longer than 10 years since no lithium battery energy is consum ed when v cc is present. see conditions of acceptability at www.maxim - ic.com/techsupport/qa/ntrl.htm clock accuracy (dip modul e) the ds1248 is guaranteed to keep time accuracy to within 1 minute per month at +25 c. the clock is calibrated at the factory by maxim using special calibration nonvolatile tuning elements and does not require additional calibration. for this reason, methods of field clock calibration are not availa ble and not necessary. clock accuracy (powercap module) the ds1248p and ds9034pcx are each individually tested for accuracy. once mounted together, the module will typically keep time accu racy to within 1.53 minutes per month (35ppm) at +25 c. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 9 of 19 absolute maximum ratings voltage range on any pin relative to ground (5v product) ..- 0.3v to +6.0v (3.3v product) .. - 0.3v to +4.6v storage temperature range edip ....................................................................................................... ................... - 40oc to +85oc powercap ...................................................................................... .................... ...... - 55c to +125c lead temperature (soldering, 10 s ) ....................................................................................... ............ +260c note: edip is wave or hand - soldered only. soldering temperature (reflow, powercap) ..................................................................... .................+ 260 c this is a stress rating only and functional operation of the device at these or any other conditions beyond those indic ated in the operation sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods of time ca n affect reliability. operating range range temp range (noncondensing) v cc (v) commercial 0c to +70c 3.3 10% or 5 10% industrial - 40c to +85c 3.3 10% or 5 10% recommended operating conditions over the operating range parameter symbol min typ max units notes logic 1 v cc = 5v 10% v ih 2.2 v cc + 0.3 v 11 v cc = 3.3v 10% 2.0 v cc + 0.3 logic 0 v cc = 5v 10% v il -0.3 +0.8 v 11 v cc = 3.3v 10% -0.3 +0.6 dc electrical characteristics over the operating range (5v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 10 ma standby current ce = v cc - 0. 5v i ccs2 3.0 5.0 ma operating current t cyc = 70ns i cc01 85 ma write protection voltage v pf 4.25 4.37 4.50 v 11 battery switchover voltage v so v bat v 11 downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 10 of 19 dc electrical characteristics over the operating range (3.3v) parameter symbol min typ max u nits notes input leakage current i il -1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 7 ma standby current ce = v cc - 0.5v i ccs2 2.0 3.0 ma operating current t cyc = 70ns i cc01 50 ma write prote ction voltage v pf 2.80 2.86 2.97 v 11 battery switchover voltage v so v bat or v pf v 11 capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf memory ac electrical characteristics over the operating range (5v) parameter symbol ds1248y-70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 50 ns 3 address setup time t aw 0 ns write recovery time t wr 0 ns output high - z from we t odw 25 ns 5 ou tput active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time from we t dh 5 ns 4 downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 11 of 19 phantom clock ac electrical characteristics over the operating range (5v) parameter symbol min typ max units notes read cycle time t rc 65 ns ce acces s time t co 55 ns oe access time t oe 55 ns ce to output low -z t coe 5 ns oe to output low -z t oee 5 ns ce to output high -z t od 25 ns 5 oe to output high -z t odo 25 ns 5 read recovery t rr 10 ns write cycle time t wc 65 ns write puls e width t wp 55 ns 3 write recovery t wr 10 ns 10 data setup time t ds 30 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 60 ns rst pulse width t rst 65 ns power - down/power - up timing over the operating range (3.3v) parameter symbol min t yp max units notes ce at v ih before power - down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t f 300 s v cc slew from v pf(min) to v so t fb 10 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t r 0 s ce at v ih after power - up t rec 1.5 2.5 ms (t a = +25c) parameter symbol min typ max units notes expected data - retention time t dr 10 years 9 warning: under no circumstances are negative undershoots of any amplitude a llowed when device is in battery - backup mode. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 12 of 19 memory ac electrical characteristics over the operating range (3.3v) para meter symbol ds1248w-120 units notes min max read cycle time t rc 120 ns access time t acc 120 ns oe to output valid t oe 60 ns ce to output valid t co 120 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 40 ns 5 output hold from address change t oh 5 ns write cycle time t wc 120 ns write pulse width t wp 90 ns 3 address setup time t aw 0 ns write recovery time t wr 20 ns 10 output high - z from we t odw 40 ns 5 output active from we t oew 5 ns 5 data set up time t ds 50 ns 4 data hold time from we t dh 20 ns 4 phantom clock ac electricalcharacteristics over the operating range (3.3v) parameter symbol min typ max units notes read cycle time t rc 120 ns ce access time t co 100 ns oe access time t oe 100 ns ce to output low -z t coe 5 ns oe to output low -z t oee 5 ns ce to output high -z t od 40 ns 5 oe to output high -z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns 3 write recove ry t wr 20 ns 10 data setup time t ds 45 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 105 ns rst pulse width t rst 120 ns downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 13 of 19 power - down/power - up timing over the operating range (3.3v) parameter symbol min typ max units notes ce at v ih bef ore power - down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t f 300 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t r 0 s ce at v ih after power - up t rec 1.5 2.5 ms (t a = +25c) parameter symbol min typ max units notes expecte d data - retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowe d when device is in battery - backup mode. memory read cycle (note 1 ) downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 14 of 19 memory write cycle 1 (notes 2, 6, and 7) memory writ e cycle 2 (notes 2 and 8) downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 15 of 19 reset for phantom clock read cycle to phantom clock write cycle to phantom clock downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 16 of 19 power - down/power - up condition (5v) power - down/power - up condition (3.3v) downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 17 of 19 ac test conditions output load: 50pf + 1ttl g ate input pulse levels: 0 to 3v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) we is high for a read cycle. 2) oe = v ih or v il . if ce = v ih during write cycle, the output buffers remain in a h igh impedance state. 3) t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4) t dh , t ds are measured from the earlier of ce or we going high. 5) these parameters are sampled with a 50pf load and are not 100% tested. 6) if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high - impedance state during this period. 7) if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high - impedance state during this period. 8) if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9) the expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. 10) t wr is a function of the latter occurring edge of we or ce . 11) voltages are referenced to gro und. 12) rst (pin 1) has an internal pullup resistor. 13) rtc modules can be successfully processed through conventional wave - soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. post - solder clea ning with water - washing techniques is acceptable, provided that ultrasonic vibration is no t used. see the powercap package drawing for details regarding the powercap packag e. downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 18 of 19 package information for the latest package outline information and land patterns (footpr ints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings ma y show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 edip mdt32 +2 21-0245 34 pwrcp pc2+3 21-0246 downloaded from: http:///
ds1248/ds1248p 1024k nv sram with phantom clock 19 of 19 maxim ca nnot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxi m product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim int egrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered tradem ark of maxim integrated products, inc. revision history revision date description pages changed 11/11 update d the features , ordering information , am/pm/12/24- mode , absolute maximum ratings , and package information sections 1, 2, 7, 9 , 18 downloaded from: http:///

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